This invention relates to semiconductor chip packaging.
Portable electronic products such as mobile telephones, mobile computers, and various consumer products require higher semiconductor functionality and performance in a limited footprint and minimal thickness and weight at the lowest cost. This has driven the industry to increase integration on the individual semiconductor chips.
More recently the industry has begun implementing integration on the “z-axis,” that is, by stacking chips, and stacks of up to five chips in one package have been used. This provides a dense chip structure having the footprint of a one-chip package, in the range of 5×5 mm to 40×40 mm, and obtaining thicknesses that have been continuously decreasing, as the technology develops, from 2.3 mm to 0.5 mm. The packaging cost for a stacked die package is only incrementally higher than the packaging cost for a single chip package, and assembly yields have been high enough to assure a competitive final cost compared to packaging the chips in individual packages.
A primary practical limitation to the number of chips that can be stacked in a stacked die package is the low final test yield of the stacked-die package. Inevitably one or more of the chips in some packages will be defective. Therefore, the final package test yield, which is the product of the individual die test yields, always will be significantly less than 100%. Where one die in a package has low yield because of design complexity or technology, final package yields can be unacceptably low even if only two die are stacked in each package.
The dimensions of the various die that may be supplied for use in a particular device can vary significantly, and this presents challenges in construction of stacked die packages. For example, in a conventional stacked die package the upper die may be a memory die and the lower die may be a digital signal processor (DSP). The assembler's favored memory die may be larger than the favored DSP die. Or, adjacent stacked die in the package may both be memory die, with the upper die being the same size as, or larger than the lower die. The yield of DSP is typically low, and where the lower die in a stacked die package is a DSP, it may be impossible in practice to test the DSP until after it is placed on the substrate; and where the DSP is wire bonded it may be impossible in practice to test the die on the substrate because the handling during testing causes damage to exposed wires. In a conventional stacked die package, therefore, the upper die must be stacked over the lower die before the lower die can be tested, and where the lower die proves at that point in the process to be unacceptable, the stacked package must be discarded, resulting in a waste both of the spacer and the upper die and of processing steps for stacking them.
Another limitation in stacked die packages is the low power dissipation capability of the package. The heat is transmitted from one die to the other and the only significant path for heat dissipation out from the package is through the solder balls to the motherboard. Conduction of heat to the ambient through the top of the package is very limited because the molding compound typically does not conduct heat well.
FIG. 1 is a diagrammatic sketch in a sectional view illustrating the structure of a conventional stacked die package having two die stacked with a spacer between them. The stacked die package, shown generally at 10, includes a first die 14 attached onto a substrate 12 having at least one metal layer, and a second 24, stacked over the first die 12, the first and second die in the stack being separated by a spacer 22.
Any of various substrate types may be used, including for example: a laminate with 2-6 metal layers, or a build up substrate with 4-8 metal layers, or a flexible polyimide tape with 1-2 metal layers, or a ceramic multilayer substrate. The substrate 12 shown by way of example in FIG. 1 has two metal layers 121, 123, on opposite sides of a dielectric 120, each metal layer being patterned to provide appropriate circuitry and connected through the dielectric by way of vias 122.
The first die 14 is conventionally attached to a surface of the substrate using an adhesive, typically referred to as the die attach epoxy, shown at 13 in FIG. 1 and, in the configuration in FIG. 1, the surface of the substrate onto which the die is attached may be referred to as the “upper” surface, and the metal layer on that surface may be referred to as the “upper” metal layer, although the die attach surface need not have any particular orientation in use. The spacer 22 is affixed to the upward-facing (active) surface of the first die 14 by an adhesive 21 and the second die 24 is affixed to the upward-facing surface of the spacer 22 by an adhesive 23.
In the stacked die package of FIG. 1 the die are wire bonded onto wire bond sites on the upper metal layer of the substrate to establish electrical connections; wire bonds 16 connect the first die 14 to the substrate and wire bonds 26 connect the second die 24 to the substrate. The die 14 and 24 and the wire bonds 16 and 26 are encapsulated (typically by array molding and saw singulation, to make a standard “chip scale package”) with a molding compound 17 that provides protection from ambient and from mechanical stress to facilitate handling operations, and provides a surface for marking for identification. Solder balls 18 are reflowed onto bonding pads on the lower metal layer of the substrate to provide interconnection to the motherboard (not shown) of a final product, such as a computer. Solder masks 125, 127 are patterned over the metal layers 121, 123 to expose the underlying metal at bonding sites for electrical connection, for example the wire bond sites and bonding pads for bonding the wire bonds 16, 26 and solder balls 18.
As will be appreciated, the wire bonds 16 have a characteristic “loop height”, which (together with a loop height tolerance) is a parameter of the wire-bonding process, and sufficient spacing must be provided between the second and the first die to avoid damage to the wire bonds by impact with the second die. Accordingly, the spacer 22 is provided as a pedestal to support the second die 24 over the first die 14. The spacer is made narrow enough so that it does not impact the wire bonds at its edges, and thick enough to provide spacing sufficient to hold the second die above the wire loops; that is, the spacer itself does not impact the wires, and it provides sufficient distance between the first and second die so that the downward-facing side of the second die does not damage the wire bonds 16.
The stacked die package as shown in FIG. 1 is well established in the industry. Such a package has a footprint as small as about 1.7 mm larger than the largest die it contains, and it can be made to a thickness profile as low as 0.8 mm to 1.4 mm. It can have lower cost compared to individually packaged die.
Contributions to the thickness of such a stacked die package by the various parts are shown by way of illustration in various two-die stacked die package configurations in the Table, following. Abbreviations such as “CT” for die thickness are placed on FIG. 1 for reference.
TABLEOverall Package Height “OT” (Max)Dimension1.4 mm1.2 mm1.0 mm0.8 mmMoldDie thickness“CT”(Max)0.1500.1320.087CapSpacer die thickness“SPT”(Max)0.1250.1250.087Loop height“LH”(Max)0.1150.0890.075Mold height“MH”(Nom)0.7000.6500.5000.370SubstrateSubstrate thickness“ST”(Nom)0.2600.2100.1900.170BallBall diameter“BD”(Nom)0.4000.3500.3500.300(option)“BD”(Nom)0.4500.3000.350Collapse height“CH”(Min)0.2500.2500.1500.150(option)“CH”(Min)0.3000.150
A principal limitation of such a structure is the low final test yield of the package, particularly if at least one die has a low yield. For instance, a memory die may be stacked over a processor die. Memory usually requires a “burn-in” test to eliminate “infant mortality”. A processor usually is a complex design, and yields of processor die are typically less than 99%. The final test yield of the package is the product of the yields of the individual die. It is possible in principle to increase the final yield by obtaining Known Good Die (“KGD”). But KGD are of limited availability and higher cost, and KGD memory die are particularly costly.
The use of a “dummy” die as a spacer, as illustrated above, requires steps of applying adhesive layers between the spacer and the die between which the spacer is interposed. There is a limit on how thin the dummy die can in practice be made, and this imposes a lower limit on the spacer die thickness. Accordingly various approaches have been suggested for providing a separation between adjacent die in stacked die packages. In some approaches a thick adhesive layer between the adjacent die provides the separation. To the extent the adhesive may collapse during the stacking process, the standoff may be difficult to control, and the planes of the adjacent die may be not be parallel. In some such approaches the spacer adhesive is filled with particles having a dimension suitable to provide the standoff between the die and to prevent die tilt. Various spacer adhesives are described in, for example, in U.S. Pat. No. 6,472,758 and U.S. Pat. No. 6,340,846, each of which is hereby incorporated herein by reference in its entirety.
Another approach to integrating on the “z-axis” is to stack die packages to form a multi-package module. Stacked packages can provide numerous advantages as compared to stacked-die packages.
For instance, each package in a stacked package module can be electrically tested, and rejected unless it shows satisfactory performance, before the packages are stacked. As a result the final stacked multi-package module yields can be maximized. While “naked” die can be tested, testing can be more readily carried out in the package, particularly where the pad pitch on the die is very small.